1. Field of the Invention
This invention relates to the testing of integrated circuits and more particularly to the testing of a large scale integrated circuits by applying an electron beam to selected additional components within the circuit.
2. Description of the Prior Art
The prior art has developed a number of techniques for positioning an electron beam with an extreme degree of accuracy. This permits electron beams to be used for fabricating semiconductor circuits. For example, an electron beam can be used to selectively expose photoresist on a mask, the mask then being useful for exposing photoresist on the surface of a semiconductor. In more sophisticated systems, the electron beam is actually used to "write" a pattern on the photoresist coated surface of a semiconductor structure. The semiconductor structure then undergoes conventional processing techniques to provide useful integrated semiconductor circuits.
The ability to accurately position an electron beam makes the fabrication of large numbers of diverse custom circuits possible. This advantage accrues from the fact that the positioning of the electron beam can be controlled by a computer program which is much more readily alterable than fixed hardware masks for the fabrication of semiconductor devices. This ability to accurately position an electron beam also permits the detection of registration marks on the semiconductor surface for purposes of positioning the beam. For example, a plurality of registration "bars" may be scanned by an electron beam and the reflected electrons may be sensed by photodetectors to accurately determine the position of the beam with respect to the registration marks.
In view of the foregoing, it was inevitable that accurately positionable electron beams would also be advantageously utilized for test purposes. For example, in U.S. Pat. No. 3,763,425 issued Oct. 2, 1973, there is disclosed a non-contact method of testing for the electrical continuity of a conductor line by means of an electron beam. U.S. Pat. No. 3,764,898 issued Oct. 9, 1973, as well as the publications cited therein, teaches a similar technique. In the latter patent, at least one end of a conductor line is bombarded with a beam of electrons. A collector is positioned in spaced proximate relation to this end of the line to control the raising of the potential at this end to a particular level due to secondary emission. Current flows through the line which is measured to indicate the state of continuity in the line.
It is noted that the known prior art techniques for testing with an E-beam operate on the principle of emission of secondary electrons. These prior art techniques do not lend themselves to the actual testing of functional circuits within an integrated circuit. Thus, although the increase of circuit density on a semiconductor chip is highly desirable because it will not only lower the cost and increase the speed but also improve the reliability of the circuit, low yield levels become a stumbling block. In accordance with presently known semiconductor processing technology, the processing of a semiconductor chip reaches a level such that as the density of the circuit further increases, the yield of such a chip will drop catastrophically. The chip yield is related to the defect density such as photolithographic defects, processing defects, and silicon crystal inherent defects. One approach to lower the cost of the chip is to improve the yield by lowering the defect density. Another approach to lower the cost is to expand the working chip yield by providing redundant circuits within a semiconductor chip. The advantages of the latter scheme, however, can only be realized with an effective nondestructive test at a relatively early stage of manufacture.